//
//  Copyright (c) 2003 Launchbird Design Systems, Inc.
//  All rights reserved.
//  
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
//    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//  
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//  
//  
//  Overview:
//  
//    Performs finite impulse response (FIR) filtering.
//    The filter's sum of products is pipelined with a register after
//    every multiplier and adder.  The adder network is a balanced binary
//    tree to minimize latency.  The sum of products has no numeric loss because the
//    multipliers keep all resulting bits and each adder extends the precision by 1.
//  
//  Interface:
//  
//    Synchronization:
//      clock_c  : Clock input.
//      reset_i  : Filter delay bank synchronous reset.  Does not reset sum of products pipeline registers.
//  
//    Inputs:
//      data_i  : Input data.
//      k0_i    : Coefficient 0 multiplied by in_i(0).
//      k1_i    : Coefficient 1 multiplied by in_i(k-1).
//      k2_i    : Coefficient 2 multiplied by in_i(k-2).
//      ...
//      k<order>_i : Coefficient <order> multiplied by in_i(k-<order>).
//  
//    Outputs:
//      data_o : Output data.
//  
//  Built In Parameters:
//  
//    Filter Order             = 24
//    Input Precision          = 16
//    Coefficient Precision    = 16
//    Sum of Products Latency  = 6
//  
//  
//  
//  
//  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com
//  
//  Build Date : Fri Aug 22 09:45:56 CDT 2003
//  
//  Interface
//  
//    Build Name    : cf_fir_24_16_16
//    Clock Domains : clock_c  
//    Vector Input  : reset_i(1)
//    Vector Input  : data_i(16)
//    Vector Input  : k0_i(16)
//    Vector Input  : k1_i(16)
//    Vector Input  : k2_i(16)
//    Vector Input  : k3_i(16)
//    Vector Input  : k4_i(16)
//    Vector Input  : k5_i(16)
//    Vector Input  : k6_i(16)
//    Vector Input  : k7_i(16)
//    Vector Input  : k8_i(16)
//    Vector Input  : k9_i(16)
//    Vector Input  : k10_i(16)
//    Vector Input  : k11_i(16)
//    Vector Input  : k12_i(16)
//    Vector Input  : k13_i(16)
//    Vector Input  : k14_i(16)
//    Vector Input  : k15_i(16)
//    Vector Input  : k16_i(16)
//    Vector Input  : k17_i(16)
//    Vector Input  : k18_i(16)
//    Vector Input  : k19_i(16)
//    Vector Input  : k20_i(16)
//    Vector Input  : k21_i(16)
//    Vector Input  : k22_i(16)
//    Vector Input  : k23_i(16)
//    Vector Input  : k24_i(16)
//    Vector Output : data_o(37)
//  
//  
//  

module cf_fir_24_16_16 (clock_c, reset_i, data_i, k0_i, k1_i, k2_i, k3_i, k4_i, k5_i, k6_i, k7_i, k8_i, k9_i, k10_i, k11_i, k12_i, k13_i, k14_i, k15_i, k16_i, k17_i, k18_i, k19_i, k20_i, k21_i, k22_i, k23_i, k24_i, data_o);
input  clock_c;
input  reset_i;
input  [15:0] data_i;
input  [15:0] k0_i;
input  [15:0] k1_i;
input  [15:0] k2_i;
input  [15:0] k3_i;
input  [15:0] k4_i;
input  [15:0] k5_i;
input  [15:0] k6_i;
input  [15:0] k7_i;
input  [15:0] k8_i;
input  [15:0] k9_i;
input  [15:0] k10_i;
input  [15:0] k11_i;
input  [15:0] k12_i;
input  [15:0] k13_i;
input  [15:0] k14_i;
input  [15:0] k15_i;
input  [15:0] k16_i;
input  [15:0] k17_i;
input  [15:0] k18_i;
input  [15:0] k19_i;
input  [15:0] k20_i;
input  [15:0] k21_i;
input  [15:0] k22_i;
input  [15:0] k23_i;
input  [15:0] k24_i;
output [36:0] data_o;
wire   [36:0] n1;
cf_fir_24_16_16_1 s1 (clock_c, reset_i, k0_i, k1_i, k2_i, k3_i, k4_i, k5_i, k6_i, k7_i, k8_i, k9_i, k10_i, k11_i, k12_i, k13_i, k14_i, k15_i, k16_i, k17_i, k18_i, k19_i, k20_i, k21_i, k22_i, k23_i, k24_i, data_i, n1);
assign data_o = n1;
endmodule

module cf_fir_24_16_16_1 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, o1);
input  clock_c;
input  i1;
input  [15:0] i2;
input  [15:0] i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
input  [15:0] i11;
input  [15:0] i12;
input  [15:0] i13;
input  [15:0] i14;
input  [15:0] i15;
input  [15:0] i16;
input  [15:0] i17;
input  [15:0] i18;
input  [15:0] i19;
input  [15:0] i20;
input  [15:0] i21;
input  [15:0] i22;
input  [15:0] i23;
input  [15:0] i24;
input  [15:0] i25;
input  [15:0] i26;
input  [15:0] i27;
output [36:0] o1;
wire   n1;
wire   n2;
wire   [36:0] s3_1;
assign n1 = 1'b1;
assign n2 = 1'b0;
cf_fir_24_16_16_2 s3 (clock_c, n1, n2, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, s3_1);
assign o1 = s3_1;
endmodule

module cf_fir_24_16_16_2 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, o1);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
input  [15:0] i11;
input  [15:0] i12;
input  [15:0] i13;
input  [15:0] i14;
input  [15:0] i15;
input  [15:0] i16;
input  [15:0] i17;
input  [15:0] i18;
input  [15:0] i19;
input  [15:0] i20;
input  [15:0] i21;
input  [15:0] i22;
input  [15:0] i23;
input  [15:0] i24;
input  [15:0] i25;
input  [15:0] i26;
input  [15:0] i27;
input  [15:0] i28;
input  [15:0] i29;
output [36:0] o1;
reg    [15:0] n1;
reg    [15:0] n2;
reg    [15:0] n3;
wire   [31:0] n4;
reg    [31:0] n5;
wire   [15:0] s6_1;
wire   [15:0] s6_2;
wire   [15:0] s6_3;
wire   [15:0] s6_4;
wire   [15:0] s6_5;
wire   [15:0] s6_6;
wire   [15:0] s6_7;
wire   [15:0] s6_8;
wire   [15:0] s6_9;
wire   [15:0] s6_10;
wire   [15:0] s6_11;
wire   [15:0] s6_12;
wire   [15:0] s6_13;
wire   [15:0] s6_14;
wire   [15:0] s6_15;
wire   [15:0] s6_16;
wire   [15:0] s6_17;
wire   [15:0] s6_18;
wire   [15:0] s6_19;
wire   [15:0] s6_20;
wire   [15:0] s6_21;
wire   [15:0] s6_22;
wire   [31:0] s7_1;
wire   [31:0] s7_2;
wire   [31:0] s7_3;
wire   [31:0] s7_4;
wire   [31:0] s7_5;
wire   [31:0] s7_6;
wire   [31:0] s7_7;
wire   [31:0] s7_8;
wire   [31:0] s7_9;
wire   [31:0] s7_10;
wire   [31:0] s7_11;
wire   [31:0] s7_12;
wire   [31:0] s7_13;
wire   [31:0] s7_14;
wire   [31:0] s7_15;
wire   [31:0] s7_16;
wire   [31:0] s7_17;
wire   [31:0] s7_18;
wire   [31:0] s7_19;
wire   [31:0] s7_20;
wire   [31:0] s7_21;
wire   [31:0] s7_22;
wire   [31:0] s7_23;
wire   [31:0] s7_24;
wire   [36:0] s8_1;
always @ (posedge clock_c)
begin
  if (i3 == 1'b1)
    n1 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n1 <= i29;
  if (i3 == 1'b1)
    n2 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i3 == 1'b1)
    n3 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n3 <= n2;
  if (i2 == 1'b1)
    n5 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n5 <= n4;
end
assign n4 = {16'b0000000000000000, i4} * {16'b0000000000000000, n1};
cf_fir_24_16_16_24 s6 (clock_c, i1, i3, n3, s6_1, s6_2, s6_3, s6_4, s6_5, s6_6, s6_7, s6_8, s6_9, s6_10, s6_11, s6_12, s6_13, s6_14, s6_15, s6_16, s6_17, s6_18, s6_19, s6_20, s6_21, s6_22);
cf_fir_24_16_16_18 s7 (clock_c, i1, i2, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, n2, n3, s6_1, s6_2, s6_3, s6_4, s6_5, s6_6, s6_7, s6_8, s6_9, s6_10, s6_11, s6_12, s6_13, s6_14, s6_15, s6_16, s6_17, s6_18, s6_19, s6_20, s6_21, s6_22, s7_1, s7_2, s7_3, s7_4, s7_5, s7_6, s7_7, s7_8, s7_9, s7_10, s7_11, s7_12, s7_13, s7_14, s7_15, s7_16, s7_17, s7_18, s7_19, s7_20, s7_21, s7_22, s7_23, s7_24);
cf_fir_24_16_16_3 s8 (clock_c, i1, i2, n5, s7_1, s7_2, s7_3, s7_4, s7_5, s7_6, s7_7, s7_8, s7_9, s7_10, s7_11, s7_12, s7_13, s7_14, s7_15, s7_16, s7_17, s7_18, s7_19, s7_20, s7_21, s7_22, s7_23, s7_24, s8_1);
assign o1 = s8_1;
endmodule

module cf_fir_24_16_16_3 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, o1);
input  clock_c;
input  i1;
input  i2;
input  [31:0] i3;
input  [31:0] i4;
input  [31:0] i5;
input  [31:0] i6;
input  [31:0] i7;
input  [31:0] i8;
input  [31:0] i9;
input  [31:0] i10;
input  [31:0] i11;
input  [31:0] i12;
input  [31:0] i13;
input  [31:0] i14;
input  [31:0] i15;
input  [31:0] i16;
input  [31:0] i17;
input  [31:0] i18;
input  [31:0] i19;
input  [31:0] i20;
input  [31:0] i21;
input  [31:0] i22;
input  [31:0] i23;
input  [31:0] i24;
input  [31:0] i25;
input  [31:0] i26;
input  [31:0] i27;
output [36:0] o1;
wire   n1;
wire   [32:0] n2;
wire   n3;
wire   [32:0] n4;
wire   [32:0] n5;
reg    [32:0] n6;
reg    dummy;
wire   [32:0] s7_1;
wire   [32:0] s7_2;
wire   [32:0] s7_3;
wire   [32:0] s7_4;
wire   [32:0] s7_5;
wire   [32:0] s7_6;
wire   [32:0] s7_7;
wire   [32:0] s7_8;
wire   [32:0] s7_9;
wire   [32:0] s7_10;
wire   [32:0] s7_11;
wire   [32:0] s7_12;
wire   [36:0] s8_1;
assign n1 = i3[31];
assign n2 = {n1, i3};
assign n3 = i4[31];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
	dummy <= 1'b0;	
  if (i2 == 1'b1)
    n6 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
end
cf_fir_24_16_16_12 s7 (clock_c, i1, i2, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, s7_1, s7_2, s7_3, s7_4, s7_5, s7_6, s7_7, s7_8, s7_9, s7_10, s7_11, s7_12);
cf_fir_24_16_16_4 s8 (clock_c, i1, i2, n6, s7_1, s7_2, s7_3, s7_4, s7_5, s7_6, s7_7, s7_8, s7_9, s7_10, s7_11, s7_12, s8_1);
assign o1 = s8_1;
endmodule

module cf_fir_24_16_16_4 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, o1);
input  clock_c;
input  i1;
input  i2;
input  [32:0] i3;
input  [32:0] i4;
input  [32:0] i5;
input  [32:0] i6;
input  [32:0] i7;
input  [32:0] i8;
input  [32:0] i9;
input  [32:0] i10;
input  [32:0] i11;
input  [32:0] i12;
input  [32:0] i13;
input  [32:0] i14;
input  [32:0] i15;
output [36:0] o1;
wire   n1;
wire   [33:0] n2;
wire   n3;
wire   [33:0] n4;
wire   [33:0] n5;
reg    [33:0] n6;
wire   [33:0] s7_1;
wire   [33:0] s7_2;
wire   [33:0] s7_3;
wire   [33:0] s7_4;
wire   [33:0] s7_5;
wire   [33:0] s7_6;
wire   [36:0] s8_1;
reg    dummy;
assign n1 = i3[32];
assign n2 = {n1, i3};
assign n3 = i4[32];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
	dummy <= 1'b0;	
  if (i2 == 1'b1)
    n6 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
end
cf_fir_24_16_16_9 s7 (clock_c, i1, i2, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, s7_1, s7_2, s7_3, s7_4, s7_5, s7_6);
cf_fir_24_16_16_5 s8 (clock_c, i1, i2, n6, s7_1, s7_2, s7_3, s7_4, s7_5, s7_6, s8_1);
assign o1 = s8_1;
endmodule

module cf_fir_24_16_16_5 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1);
input  clock_c;
input  i1;
input  i2;
input  [33:0] i3;
input  [33:0] i4;
input  [33:0] i5;
input  [33:0] i6;
input  [33:0] i7;
input  [33:0] i8;
input  [33:0] i9;
output [36:0] o1;
wire   n1;
wire   [36:0] n2;
wire   n3;
wire   [36:0] n4;
wire   [36:0] n5;
reg    [36:0] n6;
wire   [35:0] s7_1;
wire   [35:0] s7_2;
wire   [34:0] s8_1;
wire   [34:0] s8_2;
wire   [34:0] s8_3;
wire   [34:0] s8_4;
reg    dummy;
assign n1 = s7_1[35];
assign n2 = {n1, s7_1};
assign n3 = s7_2[35];
assign n4 = {n3, s7_2};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
	dummy <= 1'b0;	
  if (i2 == 1'b1)
    n6 <= 37'b0000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
end
cf_fir_24_16_16_8 s7 (clock_c, i1, i2, s8_1, s8_2, s8_3, s8_4, s7_1, s7_2);
cf_fir_24_16_16_6 s8 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, s8_1, s8_2, s8_3, s8_4);
assign o1 = n6;
endmodule

module cf_fir_24_16_16_6 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4);
input  clock_c;
input  i1;
input  i2;
input  [33:0] i3;
input  [33:0] i4;
input  [33:0] i5;
input  [33:0] i6;
input  [33:0] i7;
input  [33:0] i8;
input  [33:0] i9;
output [34:0] o1;
output [34:0] o2;
output [34:0] o3;
output [34:0] o4;
wire   n1;
wire   [34:0] n2;
wire   n3;
wire   [34:0] n4;
wire   [34:0] n5;
reg    [34:0] n6;
wire   n7;
wire   [34:0] n8;
wire   n9;
wire   [34:0] n10;
wire   [34:0] n11;
reg    [34:0] n12;
wire   [34:0] s13_1;
wire   [34:0] s13_2;
assign n1 = i3[33];
assign n2 = {n1, i3};
assign n3 = i4[33];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 35'b00000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 35'b00000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[33];
assign n8 = {n7, i5};
assign n9 = i6[33];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_7 s13 (clock_c, i1, i2, i7, i8, i9, s13_1, s13_2);
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_7 (clock_c, i1, i2, i3, i4, i5, o1, o2);
input  clock_c;
input  i1;
input  i2;
input  [33:0] i3;
input  [33:0] i4;
input  [33:0] i5;
output [34:0] o1;
output [34:0] o2;
wire   n1;
wire   [34:0] n2;
wire   n3;
wire   [34:0] n4;
wire   [34:0] n5;
reg    [34:0] n6;
wire   n7;
wire   [34:0] n8;
reg    [34:0] n9;
assign n1 = i3[33];
assign n2 = {n1, i3};
assign n3 = i4[33];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 35'b00000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n9 <= 35'b00000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n9 <= n8;
end
assign n7 = i5[33];
assign n8 = {n7, i5};
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_8 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2);
input  clock_c;
input  i1;
input  i2;
input  [34:0] i3;
input  [34:0] i4;
input  [34:0] i5;
input  [34:0] i6;
output [35:0] o1;
output [35:0] o2;
wire   n1;
wire   [35:0] n2;
wire   n3;
wire   [35:0] n4;
wire   [35:0] n5;
reg    [35:0] n6;
wire   n7;
wire   [35:0] n8;
wire   n9;
wire   [35:0] n10;
wire   [35:0] n11;
reg    [35:0] n12;
assign n1 = i3[34];
assign n2 = {n1, i3};
assign n3 = i4[34];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 36'b000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 36'b000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[34];
assign n8 = {n7, i5};
assign n9 = i6[34];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_9 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, o1, o2, o3, o4, o5, o6);
input  clock_c;
input  i1;
input  i2;
input  [32:0] i3;
input  [32:0] i4;
input  [32:0] i5;
input  [32:0] i6;
input  [32:0] i7;
input  [32:0] i8;
input  [32:0] i9;
input  [32:0] i10;
input  [32:0] i11;
input  [32:0] i12;
input  [32:0] i13;
output [33:0] o1;
output [33:0] o2;
output [33:0] o3;
output [33:0] o4;
output [33:0] o5;
output [33:0] o6;
wire   n1;
wire   [33:0] n2;
wire   n3;
wire   [33:0] n4;
wire   [33:0] n5;
reg    [33:0] n6;
wire   n7;
wire   [33:0] n8;
wire   n9;
wire   [33:0] n10;
wire   [33:0] n11;
reg    [33:0] n12;
wire   [33:0] s13_1;
wire   [33:0] s13_2;
wire   [33:0] s13_3;
wire   [33:0] s13_4;
assign n1 = i3[32];
assign n2 = {n1, i3};
assign n3 = i4[32];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[32];
assign n8 = {n7, i5};
assign n9 = i6[32];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_10 s13 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, s13_1, s13_2, s13_3, s13_4);
assign o6 = s13_4;
assign o5 = s13_3;
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_10 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4);
input  clock_c;
input  i1;
input  i2;
input  [32:0] i3;
input  [32:0] i4;
input  [32:0] i5;
input  [32:0] i6;
input  [32:0] i7;
input  [32:0] i8;
input  [32:0] i9;
output [33:0] o1;
output [33:0] o2;
output [33:0] o3;
output [33:0] o4;
wire   n1;
wire   [33:0] n2;
wire   n3;
wire   [33:0] n4;
wire   [33:0] n5;
reg    [33:0] n6;
wire   n7;
wire   [33:0] n8;
wire   n9;
wire   [33:0] n10;
wire   [33:0] n11;
reg    [33:0] n12;
wire   [33:0] s13_1;
wire   [33:0] s13_2;
assign n1 = i3[32];
assign n2 = {n1, i3};
assign n3 = i4[32];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[32];
assign n8 = {n7, i5};
assign n9 = i6[32];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_11 s13 (clock_c, i1, i2, i7, i8, i9, s13_1, s13_2);
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_11 (clock_c, i1, i2, i3, i4, i5, o1, o2);
input  clock_c;
input  i1;
input  i2;
input  [32:0] i3;
input  [32:0] i4;
input  [32:0] i5;
output [33:0] o1;
output [33:0] o2;
wire   n1;
wire   [33:0] n2;
wire   n3;
wire   [33:0] n4;
wire   [33:0] n5;
reg    [33:0] n6;
wire   n7;
wire   [33:0] n8;
reg    [33:0] n9;
assign n1 = i3[32];
assign n2 = {n1, i3};
assign n3 = i4[32];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n9 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n9 <= n8;
end
assign n7 = i5[32];
assign n8 = {n7, i5};
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_12 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12);
input  clock_c;
input  i1;
input  i2;
input  [31:0] i3;
input  [31:0] i4;
input  [31:0] i5;
input  [31:0] i6;
input  [31:0] i7;
input  [31:0] i8;
input  [31:0] i9;
input  [31:0] i10;
input  [31:0] i11;
input  [31:0] i12;
input  [31:0] i13;
input  [31:0] i14;
input  [31:0] i15;
input  [31:0] i16;
input  [31:0] i17;
input  [31:0] i18;
input  [31:0] i19;
input  [31:0] i20;
input  [31:0] i21;
input  [31:0] i22;
input  [31:0] i23;
input  [31:0] i24;
input  [31:0] i25;
output [32:0] o1;
output [32:0] o2;
output [32:0] o3;
output [32:0] o4;
output [32:0] o5;
output [32:0] o6;
output [32:0] o7;
output [32:0] o8;
output [32:0] o9;
output [32:0] o10;
output [32:0] o11;
output [32:0] o12;
wire   n1;
wire   [32:0] n2;
wire   n3;
wire   [32:0] n4;
wire   [32:0] n5;
reg    [32:0] n6;
wire   n7;
wire   [32:0] n8;
wire   n9;
wire   [32:0] n10;
wire   [32:0] n11;
reg    [32:0] n12;
wire   [32:0] s13_1;
wire   [32:0] s13_2;
wire   [32:0] s13_3;
wire   [32:0] s13_4;
wire   [32:0] s13_5;
wire   [32:0] s13_6;
wire   [32:0] s13_7;
wire   [32:0] s13_8;
wire   [32:0] s13_9;
wire   [32:0] s13_10;
assign n1 = i3[31];
assign n2 = {n1, i3};
assign n3 = i4[31];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[31];
assign n8 = {n7, i5};
assign n9 = i6[31];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_13 s13 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, s13_1, s13_2, s13_3, s13_4, s13_5, s13_6, s13_7, s13_8, s13_9, s13_10);
assign o12 = s13_10;
assign o11 = s13_9;
assign o10 = s13_8;
assign o9 = s13_7;
assign o8 = s13_6;
assign o7 = s13_5;
assign o6 = s13_4;
assign o5 = s13_3;
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_13 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10);
input  clock_c;
input  i1;
input  i2;
input  [31:0] i3;
input  [31:0] i4;
input  [31:0] i5;
input  [31:0] i6;
input  [31:0] i7;
input  [31:0] i8;
input  [31:0] i9;
input  [31:0] i10;
input  [31:0] i11;
input  [31:0] i12;
input  [31:0] i13;
input  [31:0] i14;
input  [31:0] i15;
input  [31:0] i16;
input  [31:0] i17;
input  [31:0] i18;
input  [31:0] i19;
input  [31:0] i20;
input  [31:0] i21;
output [32:0] o1;
output [32:0] o2;
output [32:0] o3;
output [32:0] o4;
output [32:0] o5;
output [32:0] o6;
output [32:0] o7;
output [32:0] o8;
output [32:0] o9;
output [32:0] o10;
wire   n1;
wire   [32:0] n2;
wire   n3;
wire   [32:0] n4;
wire   [32:0] n5;
reg    [32:0] n6;
wire   n7;
wire   [32:0] n8;
wire   n9;
wire   [32:0] n10;
wire   [32:0] n11;
reg    [32:0] n12;
wire   [32:0] s13_1;
wire   [32:0] s13_2;
wire   [32:0] s13_3;
wire   [32:0] s13_4;
wire   [32:0] s13_5;
wire   [32:0] s13_6;
wire   [32:0] s13_7;
wire   [32:0] s13_8;
assign n1 = i3[31];
assign n2 = {n1, i3};
assign n3 = i4[31];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[31];
assign n8 = {n7, i5};
assign n9 = i6[31];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_14 s13 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, s13_1, s13_2, s13_3, s13_4, s13_5, s13_6, s13_7, s13_8);
assign o10 = s13_8;
assign o9 = s13_7;
assign o8 = s13_6;
assign o7 = s13_5;
assign o6 = s13_4;
assign o5 = s13_3;
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_14 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, o1, o2, o3, o4, o5, o6, o7, o8);
input  clock_c;
input  i1;
input  i2;
input  [31:0] i3;
input  [31:0] i4;
input  [31:0] i5;
input  [31:0] i6;
input  [31:0] i7;
input  [31:0] i8;
input  [31:0] i9;
input  [31:0] i10;
input  [31:0] i11;
input  [31:0] i12;
input  [31:0] i13;
input  [31:0] i14;
input  [31:0] i15;
input  [31:0] i16;
input  [31:0] i17;
output [32:0] o1;
output [32:0] o2;
output [32:0] o3;
output [32:0] o4;
output [32:0] o5;
output [32:0] o6;
output [32:0] o7;
output [32:0] o8;
wire   n1;
wire   [32:0] n2;
wire   n3;
wire   [32:0] n4;
wire   [32:0] n5;
reg    [32:0] n6;
wire   n7;
wire   [32:0] n8;
wire   n9;
wire   [32:0] n10;
wire   [32:0] n11;
reg    [32:0] n12;
wire   [32:0] s13_1;
wire   [32:0] s13_2;
wire   [32:0] s13_3;
wire   [32:0] s13_4;
wire   [32:0] s13_5;
wire   [32:0] s13_6;
assign n1 = i3[31];
assign n2 = {n1, i3};
assign n3 = i4[31];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[31];
assign n8 = {n7, i5};
assign n9 = i6[31];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_15 s13 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, s13_1, s13_2, s13_3, s13_4, s13_5, s13_6);
assign o8 = s13_6;
assign o7 = s13_5;
assign o6 = s13_4;
assign o5 = s13_3;
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_15 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, o1, o2, o3, o4, o5, o6);
input  clock_c;
input  i1;
input  i2;
input  [31:0] i3;
input  [31:0] i4;
input  [31:0] i5;
input  [31:0] i6;
input  [31:0] i7;
input  [31:0] i8;
input  [31:0] i9;
input  [31:0] i10;
input  [31:0] i11;
input  [31:0] i12;
input  [31:0] i13;
output [32:0] o1;
output [32:0] o2;
output [32:0] o3;
output [32:0] o4;
output [32:0] o5;
output [32:0] o6;
wire   n1;
wire   [32:0] n2;
wire   n3;
wire   [32:0] n4;
wire   [32:0] n5;
reg    [32:0] n6;
wire   n7;
wire   [32:0] n8;
wire   n9;
wire   [32:0] n10;
wire   [32:0] n11;
reg    [32:0] n12;
wire   [32:0] s13_1;
wire   [32:0] s13_2;
wire   [32:0] s13_3;
wire   [32:0] s13_4;
assign n1 = i3[31];
assign n2 = {n1, i3};
assign n3 = i4[31];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[31];
assign n8 = {n7, i5};
assign n9 = i6[31];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_16 s13 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, s13_1, s13_2, s13_3, s13_4);
assign o6 = s13_4;
assign o5 = s13_3;
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_16 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4);
input  clock_c;
input  i1;
input  i2;
input  [31:0] i3;
input  [31:0] i4;
input  [31:0] i5;
input  [31:0] i6;
input  [31:0] i7;
input  [31:0] i8;
input  [31:0] i9;
output [32:0] o1;
output [32:0] o2;
output [32:0] o3;
output [32:0] o4;
wire   n1;
wire   [32:0] n2;
wire   n3;
wire   [32:0] n4;
wire   [32:0] n5;
reg    [32:0] n6;
wire   n7;
wire   [32:0] n8;
wire   n9;
wire   [32:0] n10;
wire   [32:0] n11;
reg    [32:0] n12;
wire   [32:0] s13_1;
wire   [32:0] s13_2;
assign n1 = i3[31];
assign n2 = {n1, i3};
assign n3 = i4[31];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n12 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n12 <= n11;
end
assign n7 = i5[31];
assign n8 = {n7, i5};
assign n9 = i6[31];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
cf_fir_24_16_16_17 s13 (clock_c, i1, i2, i7, i8, i9, s13_1, s13_2);
assign o4 = s13_2;
assign o3 = s13_1;
assign o2 = n12;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_17 (clock_c, i1, i2, i3, i4, i5, o1, o2);
input  clock_c;
input  i1;
input  i2;
input  [31:0] i3;
input  [31:0] i4;
input  [31:0] i5;
output [32:0] o1;
output [32:0] o2;
wire   n1;
wire   [32:0] n2;
wire   n3;
wire   [32:0] n4;
wire   [32:0] n5;
reg    [32:0] n6;
wire   n7;
wire   [32:0] n8;
reg    [32:0] n9;
assign n1 = i3[31];
assign n2 = {n1, i3};
assign n3 = i4[31];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n6 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n9 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n9 <= n8;
end
assign n7 = i5[31];
assign n8 = {n7, i5};
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fir_24_16_16_18 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21, o22, o23, o24);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
input  [15:0] i11;
input  [15:0] i12;
input  [15:0] i13;
input  [15:0] i14;
input  [15:0] i15;
input  [15:0] i16;
input  [15:0] i17;
input  [15:0] i18;
input  [15:0] i19;
input  [15:0] i20;
input  [15:0] i21;
input  [15:0] i22;
input  [15:0] i23;
input  [15:0] i24;
input  [15:0] i25;
input  [15:0] i26;
input  [15:0] i27;
input  [15:0] i28;
input  [15:0] i29;
input  [15:0] i30;
input  [15:0] i31;
input  [15:0] i32;
input  [15:0] i33;
input  [15:0] i34;
input  [15:0] i35;
input  [15:0] i36;
input  [15:0] i37;
input  [15:0] i38;
input  [15:0] i39;
input  [15:0] i40;
input  [15:0] i41;
input  [15:0] i42;
input  [15:0] i43;
input  [15:0] i44;
input  [15:0] i45;
input  [15:0] i46;
input  [15:0] i47;
input  [15:0] i48;
input  [15:0] i49;
input  [15:0] i50;
output [31:0] o1;
output [31:0] o2;
output [31:0] o3;
output [31:0] o4;
output [31:0] o5;
output [31:0] o6;
output [31:0] o7;
output [31:0] o8;
output [31:0] o9;
output [31:0] o10;
output [31:0] o11;
output [31:0] o12;
output [31:0] o13;
output [31:0] o14;
output [31:0] o15;
output [31:0] o16;
output [31:0] o17;
output [31:0] o18;
output [31:0] o19;
output [31:0] o20;
output [31:0] o21;
output [31:0] o22;
output [31:0] o23;
output [31:0] o24;
wire   [31:0] n1;
reg    [31:0] n2;
wire   [31:0] n3;
reg    [31:0] n4;
wire   [31:0] n5;
reg    [31:0] n6;
wire   [31:0] n7;
reg    [31:0] n8;
wire   [31:0] s9_1;
wire   [31:0] s9_2;
wire   [31:0] s9_3;
wire   [31:0] s9_4;
wire   [31:0] s9_5;
wire   [31:0] s9_6;
wire   [31:0] s9_7;
wire   [31:0] s9_8;
wire   [31:0] s9_9;
wire   [31:0] s9_10;
wire   [31:0] s9_11;
wire   [31:0] s9_12;
wire   [31:0] s9_13;
wire   [31:0] s9_14;
wire   [31:0] s9_15;
wire   [31:0] s9_16;
wire   [31:0] s9_17;
wire   [31:0] s9_18;
wire   [31:0] s9_19;
wire   [31:0] s9_20;
assign n1 = {16'b0000000000000000, i3} * {16'b0000000000000000, i27};
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n2 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n4 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n6 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n8 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n8 <= n7;
end
assign n3 = {16'b0000000000000000, i4} * {16'b0000000000000000, i28};
assign n5 = {16'b0000000000000000, i5} * {16'b0000000000000000, i29};
assign n7 = {16'b0000000000000000, i6} * {16'b0000000000000000, i30};
cf_fir_24_16_16_19 s9 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17, s9_18, s9_19, s9_20);
assign o24 = s9_20;
assign o23 = s9_19;
assign o22 = s9_18;
assign o21 = s9_17;
assign o20 = s9_16;
assign o19 = s9_15;
assign o18 = s9_14;
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule

module cf_fir_24_16_16_19 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
input  [15:0] i11;
input  [15:0] i12;
input  [15:0] i13;
input  [15:0] i14;
input  [15:0] i15;
input  [15:0] i16;
input  [15:0] i17;
input  [15:0] i18;
input  [15:0] i19;
input  [15:0] i20;
input  [15:0] i21;
input  [15:0] i22;
input  [15:0] i23;
input  [15:0] i24;
input  [15:0] i25;
input  [15:0] i26;
input  [15:0] i27;
input  [15:0] i28;
input  [15:0] i29;
input  [15:0] i30;
input  [15:0] i31;
input  [15:0] i32;
input  [15:0] i33;
input  [15:0] i34;
input  [15:0] i35;
input  [15:0] i36;
input  [15:0] i37;
input  [15:0] i38;
input  [15:0] i39;
input  [15:0] i40;
input  [15:0] i41;
input  [15:0] i42;
output [31:0] o1;
output [31:0] o2;
output [31:0] o3;
output [31:0] o4;
output [31:0] o5;
output [31:0] o6;
output [31:0] o7;
output [31:0] o8;
output [31:0] o9;
output [31:0] o10;
output [31:0] o11;
output [31:0] o12;
output [31:0] o13;
output [31:0] o14;
output [31:0] o15;
output [31:0] o16;
output [31:0] o17;
output [31:0] o18;
output [31:0] o19;
output [31:0] o20;
wire   [31:0] n1;
reg    [31:0] n2;
wire   [31:0] n3;
reg    [31:0] n4;
wire   [31:0] n5;
reg    [31:0] n6;
wire   [31:0] n7;
reg    [31:0] n8;
wire   [31:0] s9_1;
wire   [31:0] s9_2;
wire   [31:0] s9_3;
wire   [31:0] s9_4;
wire   [31:0] s9_5;
wire   [31:0] s9_6;
wire   [31:0] s9_7;
wire   [31:0] s9_8;
wire   [31:0] s9_9;
wire   [31:0] s9_10;
wire   [31:0] s9_11;
wire   [31:0] s9_12;
wire   [31:0] s9_13;
wire   [31:0] s9_14;
wire   [31:0] s9_15;
wire   [31:0] s9_16;
assign n1 = {16'b0000000000000000, i3} * {16'b0000000000000000, i23};
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n2 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n4 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n6 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n8 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n8 <= n7;
end
assign n3 = {16'b0000000000000000, i4} * {16'b0000000000000000, i24};
assign n5 = {16'b0000000000000000, i5} * {16'b0000000000000000, i25};
assign n7 = {16'b0000000000000000, i6} * {16'b0000000000000000, i26};
cf_fir_24_16_16_20 s9 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16);
assign o20 = s9_16;
assign o19 = s9_15;
assign o18 = s9_14;
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule

module cf_fir_24_16_16_20 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
input  [15:0] i11;
input  [15:0] i12;
input  [15:0] i13;
input  [15:0] i14;
input  [15:0] i15;
input  [15:0] i16;
input  [15:0] i17;
input  [15:0] i18;
input  [15:0] i19;
input  [15:0] i20;
input  [15:0] i21;
input  [15:0] i22;
input  [15:0] i23;
input  [15:0] i24;
input  [15:0] i25;
input  [15:0] i26;
input  [15:0] i27;
input  [15:0] i28;
input  [15:0] i29;
input  [15:0] i30;
input  [15:0] i31;
input  [15:0] i32;
input  [15:0] i33;
input  [15:0] i34;
output [31:0] o1;
output [31:0] o2;
output [31:0] o3;
output [31:0] o4;
output [31:0] o5;
output [31:0] o6;
output [31:0] o7;
output [31:0] o8;
output [31:0] o9;
output [31:0] o10;
output [31:0] o11;
output [31:0] o12;
output [31:0] o13;
output [31:0] o14;
output [31:0] o15;
output [31:0] o16;
wire   [31:0] n1;
reg    [31:0] n2;
wire   [31:0] n3;
reg    [31:0] n4;
wire   [31:0] n5;
reg    [31:0] n6;
wire   [31:0] n7;
reg    [31:0] n8;
wire   [31:0] s9_1;
wire   [31:0] s9_2;
wire   [31:0] s9_3;
wire   [31:0] s9_4;
wire   [31:0] s9_5;
wire   [31:0] s9_6;
wire   [31:0] s9_7;
wire   [31:0] s9_8;
wire   [31:0] s9_9;
wire   [31:0] s9_10;
wire   [31:0] s9_11;
wire   [31:0] s9_12;
assign n1 = {16'b0000000000000000, i3} * {16'b0000000000000000, i19};
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n2 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n4 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n6 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n8 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n8 <= n7;
end
assign n3 = {16'b0000000000000000, i4} * {16'b0000000000000000, i20};
assign n5 = {16'b0000000000000000, i5} * {16'b0000000000000000, i21};
assign n7 = {16'b0000000000000000, i6} * {16'b0000000000000000, i22};
cf_fir_24_16_16_21 s9 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12);
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule

module cf_fir_24_16_16_21 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
input  [15:0] i11;
input  [15:0] i12;
input  [15:0] i13;
input  [15:0] i14;
input  [15:0] i15;
input  [15:0] i16;
input  [15:0] i17;
input  [15:0] i18;
input  [15:0] i19;
input  [15:0] i20;
input  [15:0] i21;
input  [15:0] i22;
input  [15:0] i23;
input  [15:0] i24;
input  [15:0] i25;
input  [15:0] i26;
output [31:0] o1;
output [31:0] o2;
output [31:0] o3;
output [31:0] o4;
output [31:0] o5;
output [31:0] o6;
output [31:0] o7;
output [31:0] o8;
output [31:0] o9;
output [31:0] o10;
output [31:0] o11;
output [31:0] o12;
wire   [31:0] n1;
reg    [31:0] n2;
wire   [31:0] n3;
reg    [31:0] n4;
wire   [31:0] n5;
reg    [31:0] n6;
wire   [31:0] n7;
reg    [31:0] n8;
wire   [31:0] s9_1;
wire   [31:0] s9_2;
wire   [31:0] s9_3;
wire   [31:0] s9_4;
wire   [31:0] s9_5;
wire   [31:0] s9_6;
wire   [31:0] s9_7;
wire   [31:0] s9_8;
assign n1 = {16'b0000000000000000, i3} * {16'b0000000000000000, i15};
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n2 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n4 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n6 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n8 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n8 <= n7;
end
assign n3 = {16'b0000000000000000, i4} * {16'b0000000000000000, i16};
assign n5 = {16'b0000000000000000, i5} * {16'b0000000000000000, i17};
assign n7 = {16'b0000000000000000, i6} * {16'b0000000000000000, i18};
cf_fir_24_16_16_22 s9 (clock_c, i1, i2, i7, i8, i9, i10, i11, i12, i13, i14, i19, i20, i21, i22, i23, i24, i25, i26, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8);
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule

module cf_fir_24_16_16_22 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, o1, o2, o3, o4, o5, o6, o7, o8);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
input  [15:0] i11;
input  [15:0] i12;
input  [15:0] i13;
input  [15:0] i14;
input  [15:0] i15;
input  [15:0] i16;
input  [15:0] i17;
input  [15:0] i18;
output [31:0] o1;
output [31:0] o2;
output [31:0] o3;
output [31:0] o4;
output [31:0] o5;
output [31:0] o6;
output [31:0] o7;
output [31:0] o8;
wire   [31:0] n1;
reg    [31:0] n2;
wire   [31:0] n3;
reg    [31:0] n4;
wire   [31:0] n5;
reg    [31:0] n6;
wire   [31:0] n7;
reg    [31:0] n8;
wire   [31:0] s9_1;
wire   [31:0] s9_2;
wire   [31:0] s9_3;
wire   [31:0] s9_4;
assign n1 = {16'b0000000000000000, i3} * {16'b0000000000000000, i11};
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n2 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n4 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n6 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n8 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n8 <= n7;
end
assign n3 = {16'b0000000000000000, i4} * {16'b0000000000000000, i12};
assign n5 = {16'b0000000000000000, i5} * {16'b0000000000000000, i13};
assign n7 = {16'b0000000000000000, i6} * {16'b0000000000000000, i14};
cf_fir_24_16_16_23 s9 (clock_c, i1, i2, i7, i8, i9, i10, i15, i16, i17, i18, s9_1, s9_2, s9_3, s9_4);
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule

module cf_fir_24_16_16_23 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, o1, o2, o3, o4);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
input  [15:0] i4;
input  [15:0] i5;
input  [15:0] i6;
input  [15:0] i7;
input  [15:0] i8;
input  [15:0] i9;
input  [15:0] i10;
output [31:0] o1;
output [31:0] o2;
output [31:0] o3;
output [31:0] o4;
wire   [31:0] n1;
reg    [31:0] n2;
wire   [31:0] n3;
reg    [31:0] n4;
wire   [31:0] n5;
reg    [31:0] n6;
wire   [31:0] n7;
reg    [31:0] n8;
assign n1 = {16'b0000000000000000, i3} * {16'b0000000000000000, i7};
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n2 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n4 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n6 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n8 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n8 <= n7;
end
assign n3 = {16'b0000000000000000, i4} * {16'b0000000000000000, i8};
assign n5 = {16'b0000000000000000, i5} * {16'b0000000000000000, i9};
assign n7 = {16'b0000000000000000, i6} * {16'b0000000000000000, i10};
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule

module cf_fir_24_16_16_24 (clock_c, i1, i2, i3, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21, o22);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
output [15:0] o1;
output [15:0] o2;
output [15:0] o3;
output [15:0] o4;
output [15:0] o5;
output [15:0] o6;
output [15:0] o7;
output [15:0] o8;
output [15:0] o9;
output [15:0] o10;
output [15:0] o11;
output [15:0] o12;
output [15:0] o13;
output [15:0] o14;
output [15:0] o15;
output [15:0] o16;
output [15:0] o17;
output [15:0] o18;
output [15:0] o19;
output [15:0] o20;
output [15:0] o21;
output [15:0] o22;
reg    [15:0] n1;
reg    [15:0] n2;
reg    [15:0] n3;
reg    [15:0] n4;
reg    [15:0] n5;
reg    [15:0] n6;
reg    [15:0] n7;
wire   [15:0] s8_1;
wire   [15:0] s8_2;
wire   [15:0] s8_3;
wire   [15:0] s8_4;
wire   [15:0] s8_5;
wire   [15:0] s8_6;
wire   [15:0] s8_7;
wire   [15:0] s8_8;
wire   [15:0] s8_9;
wire   [15:0] s8_10;
wire   [15:0] s8_11;
wire   [15:0] s8_12;
wire   [15:0] s8_13;
wire   [15:0] s8_14;
wire   [15:0] s8_15;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n1 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n1 <= i3;
  if (i2 == 1'b1)
    n2 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n3 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n3 <= n2;
  if (i2 == 1'b1)
    n4 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n5 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n5 <= n4;
  if (i2 == 1'b1)
    n6 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n7 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n7 <= n6;
end
cf_fir_24_16_16_25 s8 (clock_c, i1, i2, n7, s8_1, s8_2, s8_3, s8_4, s8_5, s8_6, s8_7, s8_8, s8_9, s8_10, s8_11, s8_12, s8_13, s8_14, s8_15);
assign o22 = s8_15;
assign o21 = s8_14;
assign o20 = s8_13;
assign o19 = s8_12;
assign o18 = s8_11;
assign o17 = s8_10;
assign o16 = s8_9;
assign o15 = s8_8;
assign o14 = s8_7;
assign o13 = s8_6;
assign o12 = s8_5;
assign o11 = s8_4;
assign o10 = s8_3;
assign o9 = s8_2;
assign o8 = s8_1;
assign o7 = n7;
assign o6 = n6;
assign o5 = n5;
assign o4 = n4;
assign o3 = n3;
assign o2 = n2;
assign o1 = n1;
endmodule

module cf_fir_24_16_16_25 (clock_c, i1, i2, i3, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
output [15:0] o1;
output [15:0] o2;
output [15:0] o3;
output [15:0] o4;
output [15:0] o5;
output [15:0] o6;
output [15:0] o7;
output [15:0] o8;
output [15:0] o9;
output [15:0] o10;
output [15:0] o11;
output [15:0] o12;
output [15:0] o13;
output [15:0] o14;
output [15:0] o15;
reg    [15:0] n1;
reg    [15:0] n2;
reg    [15:0] n3;
reg    [15:0] n4;
reg    [15:0] n5;
reg    [15:0] n6;
reg    [15:0] n7;
wire   [15:0] s8_1;
wire   [15:0] s8_2;
wire   [15:0] s8_3;
wire   [15:0] s8_4;
wire   [15:0] s8_5;
wire   [15:0] s8_6;
wire   [15:0] s8_7;
wire   [15:0] s8_8;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n1 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n1 <= i3;
  if (i2 == 1'b1)
    n2 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n3 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n3 <= n2;
  if (i2 == 1'b1)
    n4 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n5 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n5 <= n4;
  if (i2 == 1'b1)
    n6 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n7 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n7 <= n6;
end
cf_fir_24_16_16_26 s8 (clock_c, i1, i2, n7, s8_1, s8_2, s8_3, s8_4, s8_5, s8_6, s8_7, s8_8);
assign o15 = s8_8;
assign o14 = s8_7;
assign o13 = s8_6;
assign o12 = s8_5;
assign o11 = s8_4;
assign o10 = s8_3;
assign o9 = s8_2;
assign o8 = s8_1;
assign o7 = n7;
assign o6 = n6;
assign o5 = n5;
assign o4 = n4;
assign o3 = n3;
assign o2 = n2;
assign o1 = n1;
endmodule

module cf_fir_24_16_16_26 (clock_c, i1, i2, i3, o1, o2, o3, o4, o5, o6, o7, o8);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
output [15:0] o1;
output [15:0] o2;
output [15:0] o3;
output [15:0] o4;
output [15:0] o5;
output [15:0] o6;
output [15:0] o7;
output [15:0] o8;
reg    [15:0] n1;
reg    [15:0] n2;
reg    [15:0] n3;
reg    [15:0] n4;
reg    [15:0] n5;
reg    [15:0] n6;
reg    [15:0] n7;
reg    [15:0] n8;
always @ (posedge clock_c)
begin
  if (i2 == 1'b1)
    n1 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n1 <= i3;
  if (i2 == 1'b1)
    n2 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n2 <= n1;
  if (i2 == 1'b1)
    n3 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n3 <= n2;
  if (i2 == 1'b1)
    n4 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n4 <= n3;
  if (i2 == 1'b1)
    n5 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n5 <= n4;
  if (i2 == 1'b1)
    n6 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n6 <= n5;
  if (i2 == 1'b1)
    n7 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n7 <= n6;
  if (i2 == 1'b1)
    n8 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n8 <= n7;
end
assign o8 = n8;
assign o7 = n7;
assign o6 = n6;
assign o5 = n5;
assign o4 = n4;
assign o3 = n3;
assign o2 = n2;
assign o1 = n1;
endmodule

